English translation for "phase locking circuit"

相位同步电路

Related Translations:

locks:  分级下脚毛簧板门锁装置，联锁装置轻熏鲑

lock:  n.1.锁，闩，栓。2.(运河等的)船闸。3.制轮楔。4.【机械工程】气闸，气塞，锁气室。5.【军事】枪机。6.锁住，固定。7.〔俚语〕拘留所。8.〔英国〕性病医院 (＝lock hospital).9.【自动化】同步。10.结合，固着。11.(摔跤的)揪扭。12.煞车。短语和例子off the lock未锁。 on the lock锁着。 trick lock(对字的)密

locked:  闭塞的堵塞的封闭的关闭的上锁的锁定，说明这里有门，需要用上开锁的工具锁定的锁机锁上的

locking:  打开或关闭文件共享锁放映机卡住封锁加锁进闸洛金锁闭锁定同步堵塞锁合锁舞同步

Example Sentences:

	1.	Dds is used to achieve fine resolution , while injection phase lock circuit is used to realize low phase noise high performance input reference frequency Dds用于实现小步进,而注入锁相电路则用来产生低相噪的高性能参考源。
	2.	Lut was replaced by the method taking triangle wave and differential in the line phase locked circuit , so it saves the hardware area and cost 在行锁相中,用取三角波然后差分的方法替换了查找表,减小了芯片面积,降低了成本。
	3.	Then according to the emphasis of the design , went deeply into the theory of pll frequency synthesizers widely used , described pll ’ s working principle , structure and several types in detail , and made research and analysis of pll frequency synthesizers ’ phase noise , including the effect of the active loop filter on the phase noise , and give some methods to make improvement as well , such as changing loop filter form , reducing divide number , and increase phase detector frequency , etc . then paper introduced the principle character and phase noise analysis of direct digital frequency synthesizer ( dds ) and injection phase lock circuit , which are also important circuits in the design 论文首先对几十年频率合成器的发展进行概述,而后针对本次设计的重点,对应用较为广泛的锁相频率合成理论进行了深入的探讨,详细介绍了锁相环的工作原理、组成结构和锁相类型,并对锁相频率合成器的相噪特性进行了研究分析,包括有源环路滤波器对于相噪的影响,提出了改善相位噪声的几点措施:改善环路形式、降低分频数、增大鉴相频率等。接着介绍了直接数字频率合成器( dds )和注入锁相电路的原理特点以及相噪分析,它们也是本次设计的重要电路。
	4.	The clock recovery block of usb2 . 0 transceiver macrocell consists of phase locked circuit , such as pll and dll ( delay locked loop ) . this block use external crystal 12mhz sin signal to produce 60mhz , 120mhz , 480mhz clock signal , and can recover colock signal form date wave . it can support 480mbps ( hs ) and 12mbps ( fs ) word speeds as defined in usb2 . 0 specification . 目的是用锁相环电路? pll和dll (延迟锁相环)实现usb2 . 0收发器宏单元utm的时钟恢复模块。其中pll环路构成的时钟发生器将外部晶振的12mhz正弦信号生成60mhz 、 120mhz 、 480mhz等本地时钟信号。 dll环路依据本地时钟信号对外部数据信号进行时钟恢复。

Similar Words：

"phase locked oscillator，plo" English translation, "phase locked pulsed oscillator，plpo" English translation, "phase locked servo system" English translation, "phase locked source" English translation, "phase locking" English translation, "phase locking technique" English translation, "phase locking unit" English translation, "phase lock，pl" English translation, "phase locus" English translation, "phase logic" English translation